library verilog;
use verilog.vl_types.all;
entity Permutation is
    port(
        Permutation_Input: in     vl_logic_vector(32 downto 1);
        Permutation_Select: in     vl_logic;
        Permutation_Output: out    vl_logic_vector(32 downto 1);
        Permutation_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Permutation;
